AMD pipeline

RAYS Studio ships a physically isolated, mathematically optimised fine-tuning pipeline for AMD hardware — RDNA and CDNA architectures on ROCm/HIP.

Why a separate path

AMD GPUs have raw compute in abundance but different roofline characteristics from NVIDIA parts: wavefront execution, distinct cache hierarchies (WMMA on RDNA3, MFMA on CDNA), and stricter memory bandwidth walls on consumer cards. A generic LoRA pipeline run on ROCm thrashes cache and launches too many kernels; targeted layer selection unlocks the silicon.

Hardware-Cooperative Layer Selection (HCLS)

• Frozen: every normalisation layer (RMSNorm, LayerNorm) and every memory-bound activation.
• Tuned: only dense GEMMs — q_proj, v_proj, gate_proj.

Wavefront-aligned matrices

AMD executes threads in wavefronts of 64. The pipeline pins the LoRA rank to exactly r = 64, so the SVD factors A and B align 1-to-1 with the execution paradigm — no register spills, no unused lanes.

Using it

Terminal:

rays --studio --amd-sync "your-model-name"

GUI:

1. Open Settings → AI Providers.
2. Select RAYS Studio.
3. Toggle AMD Hardware Fine-Tuning Pipeline.
4. Save.

Zero-copy gradient flow

Base weights stay frozen in system RAM. Only the active batch tensors, the SVD basis-restriction mask, and the tiny adapter gradient enter VRAM. Consumer 8 GB cards handle 7B models without OOMing.

Security

The AMD extension rides on top of FOGR — the low-rank deltas are routed through the aggregation daemon without ever transmitting local OSINT data.